1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory including a redundant cell for replacing a defective cell or the like.
2. Description of the Related Art
A nonvolatile semiconductor memory generally includes a redundant cell for replacing a defective cell in order to increase the yield as the memory capacity increases.
Three general types of the redundant cell are: column redundancy for relieving a defect on each bit line; row redundancy for relieving a defect on each word line; and block redundancy for relieving a defect in each block.
The types and number of redundant cells incorporated into a nonvolatile semiconductor memory are determined from various viewpoints such as the process, failure mode, chip size, and relieving ratio. Redundant cells are used most often in a period immediately after trial fabrication. In a mass-production period during which the process stabilizes, a relatively few redundant cells are used, and the use ratio also stabilizes at a low value.
Also, defects caused by data rewrite on the market exist on the order of a few ten to a few hundred ppm. Therefore, to decrease the percent defective by finding a defective cell by screening and replacing it with a redundant cell, a very long test time is necessary, and this produces an enormous test cost. Accordingly, it is practically difficult to replace a defective cell with a redundant cell by screening. As a consequence, a nonvolatile semiconductor memory (chip) is often regarded as a defective product although usable redundant cells exist in the device.
Note that as prior art relevant to the present invention, a nonvolatile memory is proposed which automatically locates a defective address, automatically determines whether the defect at the defective address is a row defect, column defect, or bit defect, and automatically replaces the defective cell with a redundant cell, thereby suppressing the increase in number of test steps and the increase in test cost (Jpn. Pat. Appln. KOKAI Publication No. 2000-57795).